Improvement in latency through the use of common buffer pool in routing node of 2D Mesh NoC

The continuous innovation of semiconductor technology enables more complex System on-Chip (SoC) designs. Tens, even hundreds of intellectual properties (IPs) are integrated into an SoC to provide various functions, including communications, networking, multimedia, storage, etc. The bus scheme connects multiple IP cores with a cost efficient shared medium. The bus-based scheme still fails to satisfy the requirements of future SoC mainly due to two major drawbacks. Non-scalable and the bandwidth is shared by all IPs and thus the bus becomes the performance bottleneck when more and more IPs are connected. In order to interconnect such a high number of elements on a die, researchers have turned to Network on Chip as a replacement to conventional shared buses and ad-hoc wiring solutions. They are attractive due to their regularity and modular design, which can lead to better routability, electrical characteristics and fault tolerance. Performance evaluation of the routing node in terms of latency is the characteristics of an efficient design of Buffer in input module. It is intended to study and quantify the behaviour of the single packet array design in relation to the multiple packet array design. The utilization efficiency of the packet buffer array improves when a common buffer is used instead of individual buffers in each input port. First Poisson’s Queuing model was prepared to manifest the differences in packet delays. The queuing model can be classified as (M/M/1); (32; FIFO). Arrival rate has been assumed to be Poisson distributed with a mean arrival rate (  ) of 10 x 10 The service rate is assumed to be exponentially distributed with a mean service rate of 10.05 x 10 6. It has been observed that latency in Common Buffer improved by 46% over its distributed buffer. A Simulink model later simulated on MATLAB to calculate the improvement in packet delay. It has been observed that the delay improved by approximately 40% through the use of a common buffer. A Verilog RTL for both common and shared buffer has been prepared and later synthesized using Design Compiler of SYNOPSYS. In distributed buffer, arrival of data packet could be delayed by 2 or 4 clock cycles which lead to latency improvement either by 17 % or 34 % in a common buffer.